Organic EL display devices are known for their thinness, high-quality image displaying capabilities and low power consumption. Organic EL display devices have a plurality of pixel circuits disposed in a matrix pattern. Each of the pixel circuits includes an organic EL element which is a self-luminous electro-optic element driven by an electric current; drive transistors; etc.
Conventionally, there is known an organic EL display device in which the pixel circuits include transistors (hereinafter called “emission control transistors”) provided therein, for controlling emission/non-emission of the organic EL element, in order to suppress abnormal emission, for example, of the organic EL element which can occur when writing a data voltage into the pixel circuit. In such an organic EL display device, a plurality of pixel circuits are formed correspondingly to a plurality of scanning lines and a plurality of emission lines. Each of the scanning lines which corresponds to one of the pixel circuits controls data voltage writing timing. Each of the emission lines which corresponds to one of the pixel circuits controls emission/non-emission timing of the organic EL element. The scanning lines are driven by a scanning driver (scanning driving section). The emission lines are driven by an emission driver (emission control driving section).
In relation to the present invention, Patent Document 1 discloses an organic EL display device in which the scanning driver and the emission driver are integrated with each other. FIG. 15 is a circuit diagram for describing the configuration of the scanning driver and the emission driver (hereinafter, these will be collectively called “scanning/emission driver” and will be indicated with a reference symbol 300) disclosed in Patent Document 1. Herein, it is assumed that there are n (n represents an integer not smaller than 2) scanning lines and n emission lines. The scanning/emission driver 300 includes a shift register 310, n first NAND gates NAND1i through NAND1n; n NOR gates NOR11 through NOR1n; and n second NAND gates NAND21 through NAND2n. The first NAND gates NAND1i (i is an integer not smaller than 1 and not greater than n) in the i-th stage receives an output SRi and an output SRi+1 from the i-th stage and the (i+1)th stage of the shift register 310 as inputs, and supplies an output based on these to the emission line EMi in the i-th row. The NOR gate NOR1i in the i-th stage receives the output SRi and the output SRi+1 in the i-th stage and the (i+1)th stage of the shift register 310 as inputs. The second NAND gate NAND2i in the i-th stage receives an output OUTi from the NOR gate 1i in the i-th stage and a clip signal CLIP as inputs, and supplies an output based on these to the scanning line Si in the i-th row. In the scanning/emission driver 300, the scanning driver is implemented by the shift register 310, the n NOR gates NOR11 through 1n, and the n second NAND gates NAND21 through 2n, whereas the emission driver is implemented by the shift register 310 and the n first NAND gates NAND11 through 1n. 